Interleaved synchronous bus access protocol for a shared memory multi-processor system
A method is described for providing asynchronous processors with inter-processor communication and access to several memory modules over a common bus which includes a first bus and a second bus, comprising: providing clock pulses on the common bus, each pulse having a period; asserting a request signal and placing priority signal on the common bus; polling the processors during the first period to determine whether the processors request access to the common bus and to determine which one processor has priority; sending a destination address from the one processor to a destination during a second period, the destination being chosen from the processors and the several memory modules; performing one of reading input data between the destination and the processor; multiplexing priority and reading input data signals on the first bus, and multiplexing address and writing output data signals on the second bus; generating poll inhibit signals prior to each reading input data signal and prior to each memory address signal preceding a writing output data operation; and queuing the input data in a first-in-first-out manner for each of the processors when the input data indicates an interprocessor interrupt.
- Assignee:
- Paradyne Corp., Largo, FL
- Patent Number(s):
- US 4797815
- OSTI ID:
- 6215196
- Resource Relation:
- Patent File Date: Filed date 22 Nov 1985
- Country of Publication:
- United States
- Language:
- English
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