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Title: PIN detector arrays and integrated readout circuitry on high-resistivity float-zone silicon

Journal Article · · IEEE Transactions on Electron Devices (Institute of Electrical and Electronics Engineers); (United States)
DOI:https://doi.org/10.1109/16.293300· OSTI ID:7046876
;  [1]; ;  [2]
  1. Stanford Univ., CA (United States). Center for Integrated Systems
  2. Univ. of Hawaii, Honolulu, HI (United States). Dept. of Physics

A new silicon PIN-diode-based pixel detector for ionizing particles integrating a two-dimensional array of detecting elements with readout circuitry has been developed and extensively tested. The signal charge is collected on a low-capacitance electrode avoiding loss of charge into the local readout circuitry within each pixel. The spatial resolution for a given circuitry size is optimized. The approach required back side patterning of the wafer, the only nonconventional part in the Stanford BiCMOS based manufacturing process. Thirteen masks on the front side of the wafer and three on the back yielded both CMOS readout circuitry and detecting elements. A gettering step helped obtain a high minority carrier lifetime (500 [mu]s). Test results obtained by infrared illumination, gamma rays, and high-energy particles, which have been described in detail elsewhere, will be summarized. They include a signal to single-channel-noise performance of about 150 to 1 for a minimum ionizing particle, which is an order of magnitude better than silicon strip detectors currently used, and a record-breaking spatial resolution in the direction of smallest pixel pitch (standard deviation of about 1.8 [mu]m). The authors describe the device and chip operation of the new detector in detail.

OSTI ID:
7046876
Journal Information:
IEEE Transactions on Electron Devices (Institute of Electrical and Electronics Engineers); (United States), Vol. 41:6; ISSN 0018-9383
Country of Publication:
United States
Language:
English