Performance analysis of multibuffered packet-switching networks in multiprocessor systems

Journal Article · Wed Feb 28 23:00:00 EST 1990 · IEEE Transactions on Computers (Institute of Electrical and Electronics Engineers); (USA)

DOI:https://doi.org/10.1109/12.48863· OSTI ID:6991565

Yoon, H ^[1]; Lee, K Y; Lui, M T ^[2]

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1. Korea Advanced Institute of Science and Technology (KR)
2. Ohio State Univ., Columbus, OH (USA)

The authors present a new analytic model and analytic results for the performance of multibuffered packet-switching interconnection networks in multiprocessor systems. previous analyses of buffered interconnection networks in the literature have assumed either single or infinite buffers as each input (or output) port of a switch. As far as multibuffered interconnection networks are concerned, only some simulation results for delta networks have been known. The authors first model single-buffered delta networks using the stat transition diagram of a buffer. The authors then extend the model to account for multiple buffers. The analytic results of multibuffered delta networks are compared to simulation results. The authors also analyze the performance of multibuffered data manipulator networks to demonstrate the generality of the model.

• OSTI ID: 6991565
• Journal Information: IEEE Transactions on Computers (Institute of Electrical and Electronics Engineers); (USA), Journal Name: IEEE Transactions on Computers (Institute of Electrical and Electronics Engineers); (USA) Vol. 39:3; ISSN ITCOB; ISSN 0018-9340
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
426000 -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ANALYTICAL SOLUTION
ARRAY PROCESSORS
COMPUTER NETWORKS
COMPUTERIZED SIMULATION
ELECTRONIC CIRCUITS
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
PARALLEL PROCESSING
PERFORMANCE TESTING
PROGRAMMING
SIMULATION
TESTING