Packet switching networks for multiprocessors and data flow computers

Journal Article · Thu Nov 01 00:00:00 EST 1984 · IEEE Trans. Comput.; (United States)

DOI:https://doi.org/10.1109/TC.1984.1676373· OSTI ID:6232371

Chin, C Y; Hwang, K

Most packet switched multistage networks have been proposed to use a unique path between any source and destination. We propose to add a few extra stages to create multiple paths between any source and destination. Connection principles of such multipath networks for packet switching are presented. Performance of such networks is analyzed for possible use in multiprocessor systems or in data flow computers. The major improvement of the proposed networks lies in significantly reduced packet wait delays in buffers, especially under heavy traffic conditions. The tradeoffs between reduced network delays and increased hardware cost are studied. Optimal design criteria and systematic procedures are provided for developing multipath packet switching networks.

• Research Organization: Corporate Research and Development, General Electric Company, Schenectady, NY
• OSTI ID: 6232371
• Journal Information: IEEE Trans. Comput.; (United States), Vol. C-33:11
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
ARRAY PROCESSORS
SWITCHING CIRCUITS
TASK SCHEDULING
DATA-FLOW PROCESSING
ARCHITECTURE
EFFICIENCY
OPTIMIZATION
PARALLEL PROCESSING
PERFORMANCE
DATA PROCESSING
ELECTRONIC CIRCUITS
PROCESSING
PROGRAMMING
990200* - Mathematics & Computers