Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers
- Purdue Univ., Lafayette, IN (USA). Ray W. Herrick Labs.
The performance of pipelined processors is limited by data dependencies and brach instructions. In order to achieve high performance, mechanisms must exist to alleviate the effects of data dependencies and branch instructions. Furthermore, in many cases, for example the support of virtual memory, it is essential interrupts be precise. In multiple functional unit pipelines processors where the instructions can complete and update the state of the machine out of program order, hardware support must be provided to implement precise interrupts. In this paper, the authors combine the problems of data dependency resolution and precise interrupt implementation. They present a design for a hardware mechanism that resolves dependencies dynamically and, at the same time, guarantees precise interrupts. Simulation studies show that, by resolving dependencies, the proposed mechanism is able to obtain a significant speedup over a simple instruction issue mechanism as well as implement precise interrupts.
- OSTI ID:
- 6937938
- Journal Information:
- IEEE Transactions on Computers (Institute of Electrical and Electronics Engineers); (USA), Vol. 39:3; ISSN 0018-9340
- Country of Publication:
- United States
- Language:
- English
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