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Title: The Wisconsin Multicube: A new large-scale cache-coherent multiprocessor

Abstract

The Wisconsin Multicube, is a large-scale, shared-memory multiprocessor architecture that employs a snooping cache protocol over a grid of buses. Each processor has a conventional (SRAM) cache optimized to minimize memory latency and a large (DRAM) snooping cache optimized to reduce bus traffic and to maintain consistency. The large snooping cache should guarantee that nearly all the traffic on the buses will be generated by I/O and accesses to shared data. The programmer's view of the system is like a multi - a set of processors having access to a common shared memory with no notion of geographical locality. Thus writing software, including the operating system, should be a straightforward extension of those techniques being developed for multis. The interconnection topology allows for a cache-coherent protocol for which most bus requests can be satisfied with no more than twice the number of bus operations required of a single-bus multi. The total symmetry guarantees that there are no topology-induced bottlenecks. The total bus bandwidth grows in proportion to the product of the number of processors and the average path length.

Authors:
;
Publication Date:
OSTI Identifier:
6933059
Resource Type:
Book
Country of Publication:
United States
Language:
English
Subject:
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; ARRAY PROCESSORS; MEMORY DEVICES; COMPUTER ARCHITECTURE; DATA TRANSMISSION; EQUIPMENT INTERFACES; COMMUNICATIONS; 990210* - Supercomputers- (1987-1989)

Citation Formats

Goodman, J R, and Woest, P J. The Wisconsin Multicube: A new large-scale cache-coherent multiprocessor. United States: N. p., 1988. Web.
Goodman, J R, & Woest, P J. The Wisconsin Multicube: A new large-scale cache-coherent multiprocessor. United States.
Goodman, J R, and Woest, P J. Fri . "The Wisconsin Multicube: A new large-scale cache-coherent multiprocessor". United States.
@article{osti_6933059,
title = {The Wisconsin Multicube: A new large-scale cache-coherent multiprocessor},
author = {Goodman, J R and Woest, P J},
abstractNote = {The Wisconsin Multicube, is a large-scale, shared-memory multiprocessor architecture that employs a snooping cache protocol over a grid of buses. Each processor has a conventional (SRAM) cache optimized to minimize memory latency and a large (DRAM) snooping cache optimized to reduce bus traffic and to maintain consistency. The large snooping cache should guarantee that nearly all the traffic on the buses will be generated by I/O and accesses to shared data. The programmer's view of the system is like a multi - a set of processors having access to a common shared memory with no notion of geographical locality. Thus writing software, including the operating system, should be a straightforward extension of those techniques being developed for multis. The interconnection topology allows for a cache-coherent protocol for which most bus requests can be satisfied with no more than twice the number of bus operations required of a single-bus multi. The total symmetry guarantees that there are no topology-induced bottlenecks. The total bus bandwidth grows in proportion to the product of the number of processors and the average path length.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1988},
month = {1}
}

Book:
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