Analysis of cache invalidation patterns in multiprocessors
To make shared-memory multiprocessors scalable, researchers are now exploring cache coherence protocols that do not rely on broadcast, but instead send invalidation messages to individual caches that contain stale data. The feasibility of such directory-based protocols is highly sensitive to the cache invalidation patterns that parallel programs exhibit. This paper analyzes the cache invalidation patterns caused by several parallel applications and investigate the effect of these patterns on a directory-based protocol. Results are based on multiprocessor traces with 4, 8 and 16 processors. To get insight into what the invalidation patterns would look like beyond 16 processors, a classification scheme is proposed for data objects found in parallel applications and link the invalidation traffic patterns observed in the traces back to these high-level objects. Results show that synchronization objects have very different invalidation patterns from those of other data objects. A write reference to a synchronization object usually causes invalidations in many more caches. Situations are noted where restructuring the application seems appropriate to reduce the invalidation traffic, and others where hardware support is more appropriate. Results also show that it should be possible to scale 'well-written' parallel programs to a large number of processors without an explosion in invalidation traffic.
- Research Organization:
- Stanford Univ., CA (USA). Computer Systems Lab.
- OSTI ID:
- 5849938
- Report Number(s):
- AD-A-207820/2/XAB
- Country of Publication:
- United States
- Language:
- English
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