An architectural model for a flat concurrent prolog processor

Book · Thu Jan 01 00:00:00 EST 1987

OSTI ID:6933002

Alkaiaj, L; Shapiro, E

The authors propose an execution model and a special-purpose processor architecture for the execution of Flat Concurrent Prolog (FCP). The execution model defines concurrency inherent to the execution of FCP on a single processor. It is derived by partitioning the FCP Sequential Abstract Machine into concurrently executing units. To support this execution model, the FCP Processor architecture consists of the following concurrent functional processors: Reduction Processor, Tag Processor, Goal Management Processor, Instruction Porcessor and Data-Trail Processor. The Goal Management Processor performs the efficient management of concurrent FCP goals reduced by the Reduction Processor. The Data-Trail Processor implements a novel cache management algorithm which supports shallow backtracking. The FCP Processor architectural model is specified in FCP itself and is part of a working simulator. The attainable performance of the FCP Processor architecture is currently under investigation.

• OSTI ID: 6933002
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
INTEGRATED CIRCUITS
COMPUTER ARCHITECTURE
PROLOG
ALGORITHMS
MEMORY DEVICES
PARALLEL PROCESSING
ELECTRONIC CIRCUITS
MATHEMATICAL LOGIC
MICROELECTRONIC CIRCUITS
PROGRAMMING
PROGRAMMING LANGUAGES
990210* - Supercomputers- (1987-1989)