Skip to main content
U.S. Department of Energy
Office of Scientific and Technical Information

Architectural support for concurrent logic programming languages

Thesis/Dissertation ·
OSTI ID:5918630
The author proposes a special-purpose processor and shared-memory multiprocessor architecture for the efficient execution of Flat Concurrent Prolog (FCP). His design method is based on the analysis of the following suspected implementation bottlenecks: the overhead of redundant clause-tries, goal suspension, activation, argument dereferencing, and clause-trailing. The analysis consists of a set of performance models that are a part of a general goal reduction model. He evaluates the models using program parameters obtained empirically by executing the System's Development Workload, which includes programs like the Logix Operating System, FCP Compiler, FCP Processor Simulator, Program Analyzer and Debugger. The most significant implementation bottleneck is the overhead of goal management. Based on the analysis, he proposes a special-purpose processor and multi-processor architecture for FCP. The processor consists of multiple concurrent functional units. The main feature is the overlapped execution of goal reduction, in the Reduction Unit, and goal management, in the Goal Management Unit. In a multiprocessor configuration, Goal Management Unit enables overlapped load balancing and goal sharing. Two simulators of FCP execution (written in FCP) were developed. The first simulates the multi-functional unit architecture, and the second the shared-memory multi-processor architecture. He evaluates the proposed architecture using analytic performance models. Using the models, he evaluates the relative execution time of functions, which enables the analysis of implementation bottlenecks. In the analysis, he also considers other workloads. Overlapped execution of goal management, and other features of the FCP processor, are also applicable to Flat Concurrent Logic Programming languages like Flat Parlog or FGHC.
Research Organization:
California Univ., Los Angeles, CA (United States)
OSTI ID:
5918630
Country of Publication:
United States
Language:
English

Similar Records

Architectural support for concurrent logic programming languages
Book · Sat Dec 31 23:00:00 EST 1988 · OSTI ID:7184662

An architectural model for a flat concurrent prolog processor
Book · Wed Dec 31 23:00:00 EST 1986 · OSTI ID:6933002

Flat parlog: a basis for comparison
Journal Article · Tue Mar 31 23:00:00 EST 1987 · Int. J. Parallel Program.; (United States) · OSTI ID:7077531