An all implanted self-aligned enhancement mode n-JFET with Zn gates for GaAs digital applications

Journal Article · Fri Jul 01 00:00:00 EDT 1994 · IEEE Electron Device Letters (Institute of Electrical and Electronics Engineers); (United States)

DOI:https://doi.org/10.1109/55.294083· OSTI ID:6929131

Sherwin, M E; Zolper, J C; Baca, A G; Shul, R J; Howard, A J; Rieger, D J; Klem, J F; Hietala, V M ^[1]

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1. Sandia National Labs., Albuquerque, NM (United States)

An all implanted self-aligned n-channel JFET fabrication process is described where Zn implantation is used to form the p[sup +] gate region. A refractory metal (W) gate contact is used to allow subsequent high temperature activation of the self-aligned Si source and drain implant. 0.7 [mu]m JFET's have a maximum transconductance of 170 mS/mm with a saturation current of 100 mA/mm at a gate bias of 0.9 V. The p[sup +]/n homojunction gate has a turn on voltage of 0.95 V at a current of 1 mA/mm. The drain-source breakdown voltage is 6.5V. Microwave measurements made at a gate bias of 1 V show an f[sub t] of 19 GHz with an f[sub max] of 36 GHz. These devices show promise for incorporation in both DCFL and complementary logic circuits.

• DOE Contract Number: AC04-94AL85000
• OSTI ID: 6929131
• Journal Information: IEEE Electron Device Letters (Institute of Electrical and Electronics Engineers); (United States), Journal Name: IEEE Electron Device Letters (Institute of Electrical and Electronics Engineers); (United States) Vol. 15:7; ISSN 0741-3106; ISSN EDLEDZ
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
426000* -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
ARSENIC COMPOUNDS
ARSENIDES
DIGITAL SYSTEMS
ELECTRICAL PROPERTIES
ELECTRONIC CIRCUITS
ELEMENTS
FABRICATION
GALLIUM ARSENIDES
GALLIUM COMPOUNDS
ION IMPLANTATION
JUNCTION TRANSISTORS
LOGIC CIRCUITS
PHYSICAL PROPERTIES
PNICTIDES
SEMICONDUCTOR DEVICES
SEMIMETALS
SILICON
TRANSISTORS