An all-implanted, self-aligned, GaAs JFET with a nonalloyed W/p[sup +]-GaAs ohmic gate contact

Journal Article · Fri Jul 01 00:00:00 EDT 1994 · IEEE Transactions on Electron Devices (Institute of Electrical and Electronics Engineers); (United States)

DOI:https://doi.org/10.1109/16.293333· OSTI ID:6913417

Zolper, J C; Baca, A G; Shul, R J; Howard, A J; Rieger, D J; Sherwin, M E; Lovejoy, M L; Hjalmarson, H P; Draper, B L; Klem, J F; Hietala, V M ^[1]

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1. Sandia National Labs., Albuquerque, NM (United States)

The authors describe a self-aligned, refractory metal gate contact, enhancement mode, GaAs junction field effect transistor (JFET) where all impurity doping was done by ion implantation. Processing conditions are presented for realizing a high gate turn on voltage ([approximately]1.0 V at 1 mA/mm of gate current) relative to GaAs MESFET's. The high gate turn-on voltage is the result of optimizing the p+-gate implant and anneal to achieve a nonalloyed ohmic contact between the implanted p[sup +]-GaAs and the sputter deposited tungsten gate contact. Initial nominally 1.0 [mu]m [times] 50 [mu]m n-JFET's have a transconductance of 85 mS/mm and f[sub t] of 11.4 GHz.

• DOE Contract Number: AC04-76DP00789
• OSTI ID: 6913417
• Journal Information: IEEE Transactions on Electron Devices (Institute of Electrical and Electronics Engineers); (United States), Journal Name: IEEE Transactions on Electron Devices (Institute of Electrical and Electronics Engineers); (United States) Vol. 41:7; ISSN 0018-9383; ISSN IETDAI
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
426000* -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
ARSENIC COMPOUNDS
ARSENIDES
DESIGN
DOPED MATERIALS
ELECTRONIC CIRCUITS
FIELD EFFECT TRANSISTORS
GALLIUM ARSENIDES
GALLIUM COMPOUNDS
GATING CIRCUITS
ION IMPLANTATION
JUNCTIONS
MATERIALS
OPERATION
PNICTIDES
SEMICONDUCTOR DEVICES
SEMICONDUCTOR JUNCTIONS
TRANSISTORS