Design considerations for a radiation hardened nonvolatile memory

Conference · Tue Nov 30 23:00:00 EST 1993 · IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States)

DOI:https://doi.org/10.1109/23.273499· OSTI ID:6908003

Murray, J R ^[1]

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1. Sandia National Labs., Albuquerque, NM (United States)

Sub-optimal design practices can reduce the radiation hardness of a circuit even though it is fabricated in a radiation hardened process. This is especially true for a nonvolatile memory, as compared to a standard digital circuit, where high voltages and unusual bias conditions are required. This paper will discuss the design technique's used in the development of a 64K EEPROM (Electrically Erasable Programmable Read Only Memory) to maximize radiation hardness. The circuit radiation test results will be reviewed in order to provide validation of the techniques.

• DOE Contract Number: AC04-76DP00789
• OSTI ID: 6908003
• Report Number(s): CONF-930704--
• Journal Information: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States), Journal Name: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States) Vol. 40:6Pt1; ISSN 0018-9499; ISSN IETNAE
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
426000 -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
440200* -- Radiation Effects on Instrument Components
Instruments
or Electronic Systems
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
DESIGN
DOSES
HARDENING
MEMORY DEVICES
PERFORMANCE TESTING
PHYSICAL RADIATION EFFECTS
RADIATION DOSES
RADIATION EFFECTS
RADIATION HARDENING
TESTING