High-bandwidth/low latency temporary storage for supercomputers

Technical Report · Tue Dec 01 04:00:00 EST 1987

OSTI ID:6890141

Swensen, J A

The traditional use of memory and symmetrical set of registers for storage of temporary results of scientific programs requires more execution time, hardware, and instruction-stream bandwidth than necessary. Novel register organizations that can be easily integrated into traditional supercomputer architectures can reduce all of these requirements. Execution speed can be more than doubled by storing temporary results in an asymmetrical set of general-purpose registers or an asymmetrical set of vector registers, instead of in memory and a small register-set. Faster access and a hardware cost one fourth that of traditional vector registers can be had by using a vector register that incorporates a pipelines, random-access-memory chip. If a large enough set of registers is used, the need to store temporary results in memory and then reload them for later use can be eliminated; this saves both instruction-stream bandwidth and execution time. 111 refs., 43 figs., 40 tabs.

• Research Organization: Lawrence Livermore National Lab., CA (USA); California Univ., Berkeley (USA). Computer Science Div.
• DOE Contract Number: W-7405-ENG-48
• OSTI ID: 6890141
• Report Number(s): UCRL-21106; UCB/CSD-87/383; ON: DE88016981
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
COMPUTER ARCHITECTURE
COMPUTERS
DATA PROCESSING
DESIGN
DIGITAL COMPUTERS
MEMORY DEVICES
MEMORY MANAGEMENT
OPTIMIZATION
PARALLEL PROCESSING
PROCESSING
PROGRAMMING
SUPERCOMPUTERS
TASK SCHEDULING