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A 4-bit Josephson data processor chip

Journal Article · · IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA)
; ; ; ; ;  [1]
  1. Central Research Lab., Hitachi Ltd., Kokubunji, Tokyo (JP)

This paper describes design and experimental results of a Josephson data processor, designed to demonstrate the possibility of a Josephson computer system with a gigahertz clock. It is a stored-program-type full processor including both a data path and a control path, and is constructed from 2066 three-junction interferometer devices on a 5 {times} 5-mm{sup 2} die. An eight-instruction set to enable the basic operations of digital signal processing is implemented. The design rule is 2.5 {mu}m. The junctions were fabricated using a Nb/AlO{sub {ital x}}/Nb process. A new latch-up-free dc flip-flop is used in the registers. A dc output buffer eliminates crosstalk from the ac power to the output signals. A stacked ac supply reduces the required ac current amplitude by one fourth. Power dissipation is 25 mW. Minimum gate delay is 9 ps. Operation could be recognized up to a 1.02 GHz clock.

OSTI ID:
6858012
Journal Information:
IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA), Journal Name: IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA) Vol. 24:5; ISSN IJSCB; ISSN 0018-9200
Country of Publication:
United States
Language:
English

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