VLSI cache RISC for the C language
Thesis/Dissertation
·
OSTI ID:6842422
The performance of computers has always been the major concern of computer architects and circuit designers. Besides their advantages of ease of design and reliability, the RISC's (Reduced Instruction Set Computers) have been able to outperform many existing computers built upon the conventional CISC (Complex Instruction Set Computer) philosophy, without the loss of high-level language support. This research presents an architectural support for a RISC in which an on-clip cache is utilized. Due to the rapidly expanding capabilities of VLSI (Very Large-Scale Integration) microelectronic circuits, a cache memory of considerable amount of storage can be embedded in the same silicon chip of the RISC CPU (central processing unit), which may greatly enhance the communications ability and access speed between the RISC and the main memory. As a result of this research, great performance improvements can be expected with the presence of the on-clip cache, and the cache does pay off for the silicon area it occupies. The implication of this research is nevertheless straightforward. It provides a basis for the VLSI design and implementation of computer systems that break away from the traditional computer architectures.
- Research Organization:
- Texas A and M Univ., College Station (USA)
- OSTI ID:
- 6842422
- Country of Publication:
- United States
- Language:
- English
Similar Records
Are RISCs ready for real-time control?
Advanced research in VLSI; Proceedings of the Fourth MIT Conference, Cambridge, MA, Apr. 7-9, 1986
Journal Article
·
Sat Nov 30 23:00:00 EST 1996
· InTech
·
OSTI ID:525881
Advanced research in VLSI; Proceedings of the Fourth MIT Conference, Cambridge, MA, Apr. 7-9, 1986
Conference
·
Tue Dec 31 23:00:00 EST 1985
·
OSTI ID:6849084