High speed parallel CRC device for concatenated data frames
This paper describes a cyclic redundancy check generator for generating cyclic redundancy check bits for each frame of input data compose of words. It comprises: data register means, having a first parallel input operatively connected to receive the input data and having a second parallel input and a parallel output, for storing transmit data to be output from the cyclic redundancy check generator; cyclic redundancy check register means, having a parallel input and a parallel output, for storing the cyclic redundancy check bits; and logic means, having an input operatively connected to the parallel outputs of the data register means and the cyclic redundancy check register means and an output operatively connected to the second parallel input of the data register means and the parallel input of the cyclic redundancy check register means, for generating updated cyclic redundancy check bits in parallel in dependence upon the transmit data from the data register means and the cyclic redundancy check bits from the cyclic redundancy check register means, for supplying the updated cyclic redundancy check bits to the cyclic redundancy check register means for storage therein and for supplying the updated cyclic redundancy check bits to the data register means for storage therein after generating the updated cyclic redundancy check bits for the last word in each frame of the input data.
- Assignee:
- Westinghouse Electric Corp., Pittsburgh, PA (USA)
- Patent Number(s):
- US 4937828; A
- Application Number:
- PPN: US s 7-267404
- OSTI ID:
- 6779597
- Country of Publication:
- United States
- Language:
- English
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