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FRISC-E; A 250-MIPS hybrid microprocessor

Journal Article · · IEEE Circuits and Devices (Institute of Electrical and Electronics Engineers); (USA)
DOI:https://doi.org/10.1109/101.55331· OSTI ID:6686320
 [1];  [2];  [3]
  1. Rensselaer Polytechnic Inst., Troy, NY (USA). Center for Integrated Electronics
  2. Rensselaer Polytechnic Inst., Troy, NY (USA). Dept. of Electrical, Computer, and Systems Engineering
  3. Tektronix, Inc., Beaverton, OR (USA)
Implementing the principles of reduced instruction set computers (RISC) with advanced high-speed circuit technology is both attractive and difficult. Advanced bipolar circuit technology, for instance, offers gate delays as low as 55 ps but dissipates considerable power. Therefore, a high-speed microprocessor fabricated with this technology must be partitioned into LSI circuits to increase yield and reduce heat flux. But partitioning requires die-to-die interconnections, which cause signal propagation delays. The authors discuss how the FRISC series of fast reduced instruction set computer designs goes a long way towards solving these problems. For FRISC-E the targeted instruction rate of 250 MIPS led to a seven-stage instruction pipeline. The authors have partitioned the processor into 11 chips.
OSTI ID:
6686320
Journal Information:
IEEE Circuits and Devices (Institute of Electrical and Electronics Engineers); (USA), Journal Name: IEEE Circuits and Devices (Institute of Electrical and Electronics Engineers); (USA) Vol. 6:3; ISSN 8755-3996; ISSN ICDME
Country of Publication:
United States
Language:
English