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A four-processor building block for SIMD processor arrays

Journal Article · · IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA)
DOI:https://doi.org/10.1109/4.52158· OSTI ID:6676009
;  [1];  [2]
  1. School of Computer Science, Carnegie Mellon Univ., Pittsburgh, PA (US)
  2. Schlumberger Research, Austin, TX (US)
A four-processor chip, for use in processor arrays for image computations, is described. The large degree of data parallelism available in image computations allows dense array implementations where all processors operate under the control of a single instruction stream. An instruction decoder shared by the four processors on the chip minimizes the pin count allocated for global control of the processors. The chip incorporates an interface to external SRAM for memory expansion with out glue chips. The full-custom 2-{mu}m CMOS chip contains 56,669 transistors and runs instructions at 10 MHz. Five hundred twelve 16-b processors and 4 megabytes of distributed external memory fit on two industry standard cards to yield 5 billion instructions power second peak throughput. As image I/O can overlap perfectly with pixel computation, an array containing 128 of these chips can provide more than 600 16-b operations per pixel on 512 {times} 512 images at 30 Hz.
OSTI ID:
6676009
Journal Information:
IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA), Journal Name: IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA) Vol. 25:2; ISSN IJSCB; ISSN 0018-9200
Country of Publication:
United States
Language:
English