The effects of problem partitioning, allocation, and granularity on the performance of multiple-processor systems
Journal Article
·
· IEEE Trans. Comput.; (United States)
In this paper the authors analyze the effects of the problem decomposition, the allocation of subproblems to processors, and the grain size of subproblems on the performance of a multiple-processor shared-memory architecture. The results indicate that for algorithms where both the computation and the communication overhead can be fully decomposed among N processors, the speedup is a nondecreasing function of the level of granularity for arbitrary interconnection structure and allocation of subproblems to processors. For these algorithms, the speedup is an increasing function of the level of granularity provided that the interconnection bandwidth is greater than unity. If the bandwidth is equal to unity, then the speedup converges to the value equal to the ratio of processing time to communication time. For algorithms where the computation is decomposable but the communication overhead cannot be decomposed, the speedup is a nondecreasing function of the level of granularity for the best case bandwidth only. If the bandwidth is less than N, the speedup reaches its maximum and then decreases approaching zero as the level of granularity grows. For algorithms where the computation consists of parallel and serial sections of code and the communication overhead is fully decomposable, the speedup converges to a value inversely proportional to the fraction of time spent in the serial code even for the best case interconnection bandwidth.
- Research Organization:
- Digital Equipment Corp., Acton, MA 01720
- OSTI ID:
- 6626840
- Journal Information:
- IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. C-36:4; ISSN ITCOB
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ALGORITHMS
ARRAY PROCESSORS
COMMUNICATIONS
COMPUTER ARCHITECTURE
DATA PROCESSING
DATA TRANSMISSION
EQUIPMENT INTERFACES
MATHEMATICAL LOGIC
MEMORY DEVICES
PARALLEL PROCESSING
PERFORMANCE
PROCESSING
PROGRAMMING
TASK SCHEDULING
TIME DEPENDENCE
990210* -- Supercomputers-- (1987-1989)
ALGORITHMS
ARRAY PROCESSORS
COMMUNICATIONS
COMPUTER ARCHITECTURE
DATA PROCESSING
DATA TRANSMISSION
EQUIPMENT INTERFACES
MATHEMATICAL LOGIC
MEMORY DEVICES
PARALLEL PROCESSING
PERFORMANCE
PROCESSING
PROGRAMMING
TASK SCHEDULING
TIME DEPENDENCE