A 70-MHz 32-b microprocessor with 1. 0-. mu. m BiCMOS macrocell library

Journal Article · Fri Jun 01 04:00:00 EDT 1990 · IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA)

DOI:https://doi.org/10.1109/4.102675· OSTI ID:6596868

Hotta, T; Bandoh, T ^[1]; Hotta, A; Nakano, T ^[2]; Iwamoto, S; Adachi, S ^[3]

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1. Hitachi Ltd., Ibaraki (Japan). Hitachi Research Lab.
2. Device Development Center, Hitachi Ltd., Tokyo (JP)
3. Asahi Works, Hitachi Ltd., Aichi (JP)

A custom 529K-transistor microprocessor with a five-stage pipeline has been implemented on a 12.98-mm{sup 2} die. Employing BiCMOS macrocells, a 32-b execution unit, extendible ROM, RAM a PLL clock generator with bipolar drivers, and sense circuits, a peak performance of 70 MIPS is achieved. Power consumption is 2.1 W at 40 MHz.

• OSTI ID: 6596868
• Journal Information: IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA), Journal Name: IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA) Vol. 25:3; ISSN 0018-9200; ISSN IJSCB
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
426000 -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
COMPUTERS
ELECTRONIC CIRCUITS
ELECTRONIC EQUIPMENT
EQUIPMENT
MEMORY DEVICES
MICROELECTRONIC CIRCUITS
MICROPROCESSORS
MOS TRANSISTORS
PERFORMANCE
SEMICONDUCTOR DEVICES
TRANSISTORS