The next generation of neural network chips

Conference · Fri Aug 01 04:00:00 EDT 1997

OSTI ID:658317

Beiu, V

There have been many national and international neural networks research initiatives: USA (DARPA, NIBS), Canada (IRIS), Japan (HFSP) and Europe (BRAIN, GALA TEA, NERVES, ELENE NERVES 2) -- just to mention a few. Recent developments in the field of neural networks, cognitive science, bioengineering and electrical engineering have made it possible to understand more about the functioning of large ensembles of identical processing elements. There are more research papers than ever proposing solutions and hardware implementations are by no means an exception. Two fields (computing and neuroscience) are interacting in ways nobody could imagine just several years ago, and -- with the advent of new technologies -- researchers are focusing on trying to copy the Brain. Such an exciting confluence may quite shortly lead to revolutionary new computers and it is the aim of this invited session to bring to light some of the challenging research aspects dealing with the hardware realizability of future intelligent chips. Present-day (conventional) technology is (still) mostly digital and, thus, occupies wider areas and consumes much more power than the solutions envisaged. The innovative algorithmic and architectural ideals should represent important breakthroughs, paving the way towards making neural network chips available to the industry at competitive prices, in relatively small packages and consuming a fraction of the power required by equivalent digital solutions.

• Research Organization: Los Alamos National Lab., NM (United States)
• Sponsoring Organization: USDOE Assistant Secretary for Management and Administration, Washington, DC (United States)
• DOE Contract Number: W-7405-ENG-36
• OSTI ID: 658317
• Report Number(s): LA-UR--97-1917; CONF-980216--; ON: DE97008148
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
ALGORITHMS
ANALOG SYSTEMS
DIGITAL SYSTEMS
IMPLEMENTATION
INTEGRATED CIRCUITS
LEARNING
NEURAL NETWORKS