Control scheme for microcomputers being used in multiprocessor arrays
Conference
·
OSTI ID:6564730
In general, microcomputer central processor devices are completely controllable from memory and memory control lines. By interjecting a controlling processor between the central processor chip and its memory, and using the central processor memory ready signal for synchronization, data can be supplied to the microprocessor either from an attached memory or from the controlling processor. The controlling processor may also download codes into the microprocessor's memory to be used either as programs or as data. By manipulating restart, hold and interrupt signal lines in addition to the memory lines, total control is achieved. Such a scheme can be used to orchestrate the simultaneous application of arrays of microcomputers to single large problems or to many discrete smaller problems. We describe the details of such connections to three commercially available devices: a Motorola 68000, an Advanced Micro Devices 29116 and a National Semiconductor NS32032 and indicate how our scheme may be used to connect such devices into a cooperating parallel array.
- Research Organization:
- Lawrence Berkeley Lab., CA (USA)
- DOE Contract Number:
- AC03-76SF00098
- OSTI ID:
- 6564730
- Report Number(s):
- LBL-17607; CONF-8406163-1; ON: DE84014590
- Country of Publication:
- United States
- Language:
- English
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