CMOS hardness assurance through process controls and optimized design procedures

Conference · Thu Dec 01 04:00:00 EST 1977 · IEEE Trans. Nucl. Sci.; (United States)

OSTI ID:6545887

Sanders, T J

Total Dose Hardness Assurance for complimentary MOS integrated circuits is recognized throughout the industry as a difficult problem. Most of the hardness assurance proposals to date have included a large amount of radiation testing on a diffusion lot or wafer basis to help guarantee the hardness of a small group of integrated circuits. This, in general, is very expensive, and alternate techniques must be explored. This paper discusses the use of process and device parameter controls along with optimized design procedures for radiation hardness to minimize the need for frequent radiation testing. Total dose data up to 1 x 10/sup 6/ Rads-Si are presented for several metal gate CMOS diffusion lots which demonstrate the reproducibility obtained when these control and design procedures are implemented.

• Research Organization: Harris Semiconductor, Melbourne, FL
• OSTI ID: 6545887
• Conference Information: Journal Name: IEEE Trans. Nucl. Sci.; (United States) Journal Volume: NS-24:6
• Country of Publication: United States
• Language: English

Related Subjects

440200* -- Radiation Effects on Instrument Components
Instruments
or Electronic Systems
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
ELECTRONIC CIRCUITS
HARDENING
INTEGRATED CIRCUITS
MANUFACTURING
MICROELECTRONIC CIRCUITS
MOS TRANSISTORS
PERFORMANCE TESTING
PHYSICAL RADIATION EFFECTS
QUALITY ASSURANCE
RADIATION EFFECTS
RADIATION HARDENING
SEMICONDUCTOR DEVICES
TESTING
TRANSISTORS