Best first search algorithm for optimal PLA folding and its implementation on virtual bit map processor

Thesis/Dissertation · Wed Jan 01 04:00:00 EST 1986

OSTI ID:6471786

Hwang, S Y

Folding is a PLA optimization technique that constructs a physical PLA that minimizes silicon area by structural reorganization, exploiting a particular input and output format of the PLA. The technique entails the physical splitting of a line into two or more segments so that different signals may share a single vertical (or horizontal) track. The objective of a folding algorithm is to determine the permutations of rows and/or columns that permit a maximal set of columns and/or rows to be implemented in a physical line, such that the original functions can be implemented in the smallest physical array. This thesis also addresses the algorithm design on a bit slice, two dimensional array VLSI computing structure, called the Virtual Bit Map Processor (VBMP), for the implementation of the proposed algorithm. Utilizing the unique features of the VBMP to handle the bit map data, such as virtual data mapping capability, columnwise and rowwise global memories, and regional and data dependent masking schemes for execution control of each processing element, several classes of algorithms are designed, which include data manipulating functions, graph and associative search algorithms. The use of the VBMP system to solve several classes of problems is discussed.

• Research Organization: Stanford Univ., CA (USA)
• OSTI ID: 6471786
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ALGORITHMS
ARRAY PROCESSORS
DESIGN
ELECTRONIC CIRCUITS
IMPLEMENTATION
INTEGRATED CIRCUITS
MAPPING
MATHEMATICAL LOGIC
MICROELECTRONIC CIRCUITS