A methodology to study lateral parasitic transistors in CMOS technologies

Journal Article · Mon Jun 01 00:00:00 EDT 1998 · IEEE Transactions on Nuclear Science

DOI:https://doi.org/10.1109/23.685211· OSTI ID:644132

Flament, O; Chabrerie, C; Ferlet-Cavrois, V; Leray, J L ^[1]; Faccio, F; Jarron, P ^[2]

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1. CEA Centre d`Etudes, Bruyeres-le-Chatel (France)
2. CERN, Geneva (Switzerland)

This work concerns the development of a methodology specially devoted to lateral parasitic transistors that limit the total dose hardness of CMOS technologies. This methodology is based on (i) the irradiation of standard NMOS transistors followed by (ii) isochronal annealing measurements to determine energetic spectra of the field oxide trapped charge. Post irradiation effects have been evaluated through additional isothermal annealing experiments at 75 C which are consistent with isochronal results. The authors propose a test procedure which allows to determine physical parameters helpful to improve comparison and qualification of CMOS commercial technologies.

• OSTI ID: 644132
• Report Number(s): CONF-970934-; ISSN 0018-9499; TRN: 98:008065
• Journal Information: IEEE Transactions on Nuclear Science, Vol. 45, Issue 3Pt3; Conference: RADECS 97: radiations and their effects on devices and systems conference, Cannes (France), 15-19 Sep 1997; Other Information: PBD: Jun 1998
• Country of Publication: United States
• Language: English

Related Subjects

44 INSTRUMENTATION
INCLUDING NUCLEAR AND PARTICLE DETECTORS
MOS TRANSISTORS
RADIATION HARDENING
ANNEALING
TRAPPING
PHYSICAL RADIATION EFFECTS