Efficient code generation for horizontal architectures: compiler techniques and architectural support
A horizontal architecture consists of a number of resources which can operate in parallel and each of which is controlled by a field in the wide instruction word. Such architectures offer the potential for high performance scientific computing at a modest cost. If this potential performance is to be realised, the multiple resources of a horizontal processor must be scheduled effectively. The scheduling task for conventional horizontal processors is quite complex and the construction of highly optimising compilers for them is a difficult and expensive project. The polycyclic architecture is a horizontal architecture with architectural support for the scheduling task. The complexity of scheduling conventional horizontal processors and the ease of scheduling polycyclic processors is demonstrated by means of an example. 17 references.
- OSTI ID:
- 6421991
- Resource Relation:
- Conference: Sponsored by IEEE, Austin, TX, USA, 26 Apr 1982
- Country of Publication:
- United States
- Language:
- English
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