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An SEU tolerant memory cell derived from fundamental studies of SEU mechanisms in SRAM

Conference ·
OSTI ID:6416657

Novel SEU experiments and advanced simulations are used to prove the feasibility of a new memory hardening scheme. Resistors are configured within the memory cell (1) to voltage divide the longer SEU induced transients at the information nodes, as well as, (2) to delay these transients by the conventional resistive decoupling technique.

Research Organization:
Sandia National Labs., Albuquerque, NM (USA); Hughes Research, Carlsbad, CA (USA)
DOE Contract Number:
AC04-76DP00789
OSTI ID:
6416657
Report Number(s):
SAND-87-0337C; CONF-870724-4; ON: DE87005858
Country of Publication:
United States
Language:
English