Architecture of a golay-logic image processor
Book
·
OSTI ID:6412443
The authors describe a new, microprocessor-controlled golay image processor. Capable of processing binary pixels at the rate of one per 25 ns, the processor can apply a transform cycle to a complete 64*64-pixel image in 100 mus, and its architecture permits expansion to larger image formats while retaining a future option of applying golay operations to grey-level images. The processor is used in clinical instrumentation for real-time analysis of cell images, as well as in an independent form for interactive development and evaluation of feature extraction algorithms for use in such applications. The microprocessor totally controls image processing activities in both forms, eliminating need for interface circuitry to decode golay logic instructions. Although originating in support of cell classification, processor hardware is not defined by this application, and its parallel-processing power can be applied to images from many areas of interest. 12 references.
- OSTI ID:
- 6412443
- Country of Publication:
- United States
- Language:
- English
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