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Title: Simulation of parallel random access machines by circuits

Abstract

A relationship is established between (i) parallel random-access machines that allow many processors to concurrently read from or write into a common memory including simultaneous reading or writing into the same memory location (CRCW PRAM), and (ii) combinational logic circuits that contain AND's, OR's and NOT's, with no bound placed on the fan-in of AND-gates and OR-gates. Parallel time and number of processors for CRCW PRAM's are shown to correspond respectively (and simulaneously) to depth and size for circuits, where the time-depth correspondence is to within a constant factor and the processors-size correspondence is to within a polynomial. By applying a recent result of Furst, Saxe and Sipser, the authors obtain the corollary that parity, integer multiplication, graph transitive closure and integer sorting cannot be computed in constant time by a CRCW PRAM with a polynomial number of processors. This is the first nonconstant lower bound on the parallel time required to solve these problems by a CRCW PRAM with a polynomial number of processors. The authors also state and outline the proof of a similar result, due to W. L. Ruzzo and M. Tompa, that relates time and processor bounds for CRCW PRAM's to alternation and space bounds formore » alternating Turing machines.« less

Authors:
;
Publication Date:
Research Org.:
IBM Res. Lab., San Jose, CA
OSTI Identifier:
6300636
Resource Type:
Journal Article
Journal Name:
SIAM J. Comput.; (United States)
Additional Journal Information:
Journal Volume: 13:2
Country of Publication:
United States
Language:
English
Subject:
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; PARALLEL PROCESSING; BOUNDARY CONDITIONS; DIGITAL COMPUTERS; SIMULATION; TIME DEPENDENCE; COMPUTER CALCULATIONS; LIMITING VALUES; LOGIC CIRCUITS; MEMORY DEVICES; COMPUTERS; ELECTRONIC CIRCUITS; PROGRAMMING; 990200* - Mathematics & Computers

Citation Formats

Stockmeyer, L., and Vishkin, U. Simulation of parallel random access machines by circuits. United States: N. p., 1984. Web. doi:10.1137/0213027.
Stockmeyer, L., & Vishkin, U. Simulation of parallel random access machines by circuits. United States. doi:10.1137/0213027.
Stockmeyer, L., and Vishkin, U. Tue . "Simulation of parallel random access machines by circuits". United States. doi:10.1137/0213027.
@article{osti_6300636,
title = {Simulation of parallel random access machines by circuits},
author = {Stockmeyer, L. and Vishkin, U.},
abstractNote = {A relationship is established between (i) parallel random-access machines that allow many processors to concurrently read from or write into a common memory including simultaneous reading or writing into the same memory location (CRCW PRAM), and (ii) combinational logic circuits that contain AND's, OR's and NOT's, with no bound placed on the fan-in of AND-gates and OR-gates. Parallel time and number of processors for CRCW PRAM's are shown to correspond respectively (and simulaneously) to depth and size for circuits, where the time-depth correspondence is to within a constant factor and the processors-size correspondence is to within a polynomial. By applying a recent result of Furst, Saxe and Sipser, the authors obtain the corollary that parity, integer multiplication, graph transitive closure and integer sorting cannot be computed in constant time by a CRCW PRAM with a polynomial number of processors. This is the first nonconstant lower bound on the parallel time required to solve these problems by a CRCW PRAM with a polynomial number of processors. The authors also state and outline the proof of a similar result, due to W. L. Ruzzo and M. Tompa, that relates time and processor bounds for CRCW PRAM's to alternation and space bounds for alternating Turing machines.},
doi = {10.1137/0213027},
journal = {SIAM J. Comput.; (United States)},
number = ,
volume = 13:2,
place = {United States},
year = {1984},
month = {5}
}