Simulation of parallel random access machines by circuits

Journal Article · Tue May 01 04:00:00 EDT 1984 · SIAM J. Comput.; (United States)

DOI:https://doi.org/10.1137/0213027· OSTI ID:6300636

Stockmeyer, L; Vishkin, U

A relationship is established between (i) parallel random-access machines that allow many processors to concurrently read from or write into a common memory including simultaneous reading or writing into the same memory location (CRCW PRAM), and (ii) combinational logic circuits that contain AND's, OR's and NOT's, with no bound placed on the fan-in of AND-gates and OR-gates. Parallel time and number of processors for CRCW PRAM's are shown to correspond respectively (and simulaneously) to depth and size for circuits, where the time-depth correspondence is to within a constant factor and the processors-size correspondence is to within a polynomial. By applying a recent result of Furst, Saxe and Sipser, the authors obtain the corollary that parity, integer multiplication, graph transitive closure and integer sorting cannot be computed in constant time by a CRCW PRAM with a polynomial number of processors. This is the first nonconstant lower bound on the parallel time required to solve these problems by a CRCW PRAM with a polynomial number of processors. The authors also state and outline the proof of a similar result, due to W. L. Ruzzo and M. Tompa, that relates time and processor bounds for CRCW PRAM's to alternation and space bounds for alternating Turing machines.

• Research Organization: IBM Res. Lab., San Jose, CA
• OSTI ID: 6300636
• Journal Information: SIAM J. Comput.; (United States), Journal Name: SIAM J. Comput.; (United States) Vol. 13:2; ISSN SMJCA
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
BOUNDARY CONDITIONS
COMPUTER CALCULATIONS
COMPUTERS
DIGITAL COMPUTERS
ELECTRONIC CIRCUITS
LIMITING VALUES
LOGIC CIRCUITS
MEMORY DEVICES
PARALLEL PROCESSING
PROGRAMMING
SIMULATION
TIME DEPENDENCE