Partitioned matrix algorithms for VLSI arithmetic systems
Journal Article
·
· IEEE Trans. Comput.; (United States)
A new class of partitioned matrix algorithms is developed for possible VLSI implementation of large-scale matrix solvers. Fast matrix solvers are higherly demanded in signal/image processing and in many real-time and scientific applications. Only a few functional types of VLSI arithmetic chips are needed for submatrix computations after partitioning. This partitioned approach is not restricted by problem sizes and thus can be applied to solve arbitrarily large linear systems of equations in an iterative fashion. Architectural design tradeoffs, application requirements, and performance assessment of the proposed VLSI matrix computing structures are also provided. 18 references.
- Research Organization:
- Purdue Univ., West Lafayette, IN
- OSTI ID:
- 6282473
- Journal Information:
- IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. 12; ISSN ITCOB
- Country of Publication:
- United States
- Language:
- English
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