Buried layer/connecting layer high energy implantation for improved CMOS latch-up
- Silicon Engineering, Austin, TX (United States)
- Eaton Corporation, Beverly, MA (United States)
- Advanced Micro Devices, Austin, TX (United States)
An integrated P-Buried Layer formed by MeV ion implantation combined with a localized P-Connecting Layer has been studied for latch-up isolation improvements for advanced CMOS technology. Latch-up trigger currents have been characterized with regards to buried layer dose/energy, connecting layer dose/energy, and n-well retrograde dose. Simulation results confirmed by data indicate that P+ injection trigger currents > 450 {mu}A/{mu}m can be achieved by utilizing certain combinations of B.L./C.L. and n-well retrograde doses for n+/p+ spacings = 2.0{mu}m. The B.L./C.L. process architecture shows great promise for providing an alternative isolation technique for latch-up improvement that is easy to implement, and for eliminating the dependence on epi silicon for latch-up control.
- OSTI ID:
- 621337
- Report Number(s):
- CONF-9606110--
- Country of Publication:
- United States
- Language:
- English
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