Josephson 32-bit shift register

Conference · Thu Feb 28 23:00:00 EST 1991 · IEEE Transactions on Magnetics (Institute of Electrical and Electronics Engineers); (United States)

OSTI ID:6092610

Yuh, P F; Yao, C T; Bradley, P ^[1]

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1. Hypres, Inc., Elmsford, NY (United States)

This paper reports on a 32-bit shift register designed by edge-triggered gates tested with {plus minus}25% bias margin and {plus minus}81% input margin for the full array. Simulations have shown {plus minus}55% bias margin at 3.3 GHz and working up to a maximum frequency of 30 GHz with a junction current density of 2000A/cm{sup 2} although the shift register has only been tested up to 500 MHz, limited by instrumentation. This edge-triggered gate consisting of a pair of conventional Josephson logic gates in series has the advantages of wide margins, short reset time, and insensitivity to global parameter-variations.

• OSTI ID: 6092610
• Report Number(s): CONF-900944--
• Journal Information: IEEE Transactions on Magnetics (Institute of Electrical and Electronics Engineers); (United States), Journal Name: IEEE Transactions on Magnetics (Institute of Electrical and Electronics Engineers); (United States) Vol. 27:2; ISSN IEMGA; ISSN 0018-9464
• Country of Publication: United States
• Language: English

Related Subjects

665411 -- Basic Superconductivity Studies-- (1992-)
665412* -- Superconducting Devices-- (1992-)
75 CONDENSED MATTER PHYSICS
SUPERCONDUCTIVITY AND SUPERFLUIDITY
99 GENERAL AND MISCELLANEOUS
990200 -- Mathematics & Computers
COMPUTERIZED SIMULATION
CRYSTAL DEFECTS
CRYSTAL STRUCTURE
CURRENT DENSITY
DESIGN
DISLOCATIONS
EDGE DISLOCATIONS
ELECTRONIC CIRCUITS
JOSEPHSON JUNCTIONS
JUNCTIONS
LINE DEFECTS
LOGIC CIRCUITS
PARAMETRIC ANALYSIS
SIMULATION
SUPERCONDUCTING JUNCTIONS