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Josephson shift register design and layout

Conference · · IEEE Trans. Magn.; (United States)
OSTI ID:6043747
; ;

Integrated circuit chips were designed and fabricated, based on Josephson shift register circuit that simulated operation at 25 GHz using the SPICE program. The 6.25 mm square chip featured a twelve-gate, four-stage shift register fabricated with Nb/AlO/sub x//Nb Josephson junctions with a design value of 2000 A/cm/sup 2/ critical current density. SUPERCOMPACT, a general program for the design of monolithic microwave integrated circuits, was used to model the effects of layout geometry on the uniformity and phase coherence of logic gate bias currents. Gate bias resistors were treated as resistive transmission lines. A layout geometry for the superconductive transmission lines and thin film bias resistors was developed. The original SPICE-designed circuit was modified as a result of these calculations. Modeling indicated that bias current variations could be limited to 3% for all possible logic states of the shift register, and phase coherence of the gates could be maintained to within 2 degrees of 10 Ghz. The fundamental soundness of the circuit design was demonstrated by the proper operation of fabricated shift registers.

Research Organization:
Westinghouse R and D Center, Pittsburgh, PA (US); Intermagnetics General Corp., Guilderland, NY (US)
OSTI ID:
6043747
Report Number(s):
CONF-880812-
Journal Information:
IEEE Trans. Magn.; (United States), Journal Name: IEEE Trans. Magn.; (United States) Vol. 25:2; ISSN IEMGA
Country of Publication:
United States
Language:
English

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