Parallel depth first search. Part II. Analysis
Journal Article
·
· Int. J. Parallel Program.; (United States)
This paper presents the analysis of a parallel formulation of depth-first search. At the heart of this parallel formulation is a dynamic work-distribution scheme that divides the work between different processors. The effectiveness of the parallel formulation is strongly influenced by the work-distribution scheme and the target architecture. The authors introduce the concept of isoefficiency function to characterize the effectiveness of different architectures and work-distribution schemes. Many researchers considered the ring architecture to be quite suitable for parallel depth-first search. Their analytical and experimental results show that hypercube and shared-memory architectures are significantly better. The analysis of previously known work-distribution schemes motivated the design of substantially improved schemes for ring and shared-memory architectures. In particular, they present a work-distribution algorithm that guarantees close to optimal performance on a shared-memory/omega-network-with-message-combining architecture (e.g. RP3). Much of the analysis presented in this paper is applicable to other parallel algorithms in which work is dynamically shared between different processors (e.g., parallel divide-and-conquer algorithms). The concept of isoefficiency is useful in characterizing the scalability of a variety of parallel algorithms.
- OSTI ID:
- 6062660
- Journal Information:
- Int. J. Parallel Program.; (United States), Journal Name: Int. J. Parallel Program.; (United States) Vol. 16:6; ISSN IJPPE
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ALGORITHMS
ARRAY PROCESSORS
COMMUNICATIONS
COMPUTER ARCHITECTURE
COMPUTER CODES
DATA PROCESSING
DATA TRANSMISSION
EFFICIENCY
FUNCTIONS
MATHEMATICAL LOGIC
MATHEMATICAL MODELS
MEMORY DEVICES
PARALLEL PROCESSING
PERFORMANCE
POLYNOMIALS
PROCESSING
PROGRAMMING
SYSTEMS ANALYSIS
TASK SCHEDULING
990210* -- Supercomputers-- (1987-1989)
ALGORITHMS
ARRAY PROCESSORS
COMMUNICATIONS
COMPUTER ARCHITECTURE
COMPUTER CODES
DATA PROCESSING
DATA TRANSMISSION
EFFICIENCY
FUNCTIONS
MATHEMATICAL LOGIC
MATHEMATICAL MODELS
MEMORY DEVICES
PARALLEL PROCESSING
PERFORMANCE
POLYNOMIALS
PROCESSING
PROGRAMMING
SYSTEMS ANALYSIS
TASK SCHEDULING