Area-time efficient and fault-tolerant VLSI arrays for digital signal processing
Thesis/Dissertation
·
OSTI ID:6046201
Very Large Scale Integration (VLSI) technology holds the potential to achieve immense computational throughput, but that achievement is hindered by high design cost, high manufacturing cost, and low reliability. The use of algorithmically-specialized integrated-circuits and Algorithm-Based Fault-Tolerance (ABFT) largely redresses these difficulties for many diverse signal processing problems. ABFT is used with array architectures to increase manufacturing yield and run-time reliability. In this thesis, new external communication lower-bounds based on input-output constraints are derived for the VLSI model. A new calculation lower bond based on a hybrid of sequential complexity theory and VLSI complexity theory is derived. New lower bounds with corresponding tight upper-bound constructions are presented for a wide variety of problems characterized by generalized matrix-vector recursions, which include maximum-a-posteriori (MAP) sequence estimation problems, such as Viterbi decoding and tracking phase-jitter in phase-shift-keying. The modular and locally connected systolic arrays are shown to be special cases of area-time efficiency in VLSI complexity theory.
- Research Organization:
- Colorado Univ., Boulder, CO (USA)
- OSTI ID:
- 6046201
- Country of Publication:
- United States
- Language:
- English
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