RSFQ logic arithmetic

Conference · Tue Feb 28 23:00:00 EST 1989 · IEEE Trans. Magn.; (United States)

OSTI ID:6043768

Mukhanov, O A; Rylov, S V; Semenov, V K; Vyshenskii, S V

Several ways of local timing of the Josephson-junction RSFQ (Rapid Single Flux Quantum) logic elements are proposed, and their peculiarities are discussed. Several examples of serial and parallel pipelined arithmetic blocks using various types of timing are suggested and their possible performance is discussed. Serial devices enable one to perform n-bit functions relatively slowly but using integrated circuits of a moderate integration scale, while parallel pipelined devices are more hardware-wasteful but promise extremely high productivity.

• Research Organization: Dept. of Physics, Moscow State Univ., Moscow (SU)
• OSTI ID: 6043768
• Report Number(s): CONF-880812-
• Journal Information: IEEE Trans. Magn.; (United States), Journal Name: IEEE Trans. Magn.; (United States) Vol. 25:2; ISSN IEMGA
• Country of Publication: United States
• Language: English

Related Subjects

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71 CLASSICAL AND QUANTUM MECHANICS
GENERAL PHYSICS
COMPUTER CODES
ELECTRONIC CIRCUITS
INTEGRATED CIRCUITS
JOSEPHSON JUNCTIONS
JUNCTIONS
LOGIC CIRCUITS
MECHANICS
MICROELECTRONIC CIRCUITS
PERFORMANCE
QUANTUM MECHANICS
SUPERCONDUCTING JUNCTIONS