Method and apparatus for synchronizing clocks prior to the execution of a flush operation
Patent
·
OSTI ID:6024729
A multiprocessor system is described which includes a clock signal energizing the processor and a different clock signal energizing the main memory, comprising: synchronizing means for synchronizing the clock signal energizing the second processor with the different signal energizing the main memory; and means for flushing the desired page of data from the cache of the second processor to the main memory for storage therein when the synchronizing means completes the synchronization of the clock signal energizing the second processor with the clock signal energizing the main memory, the desired page of data stored in the main memory being utilized by the first processor in the execution of an instruction.
- Assignee:
- International Business Machines Corp., Armonk, NY
- Patent Number(s):
- US 4827401
- OSTI ID:
- 6024729
- Country of Publication:
- United States
- Language:
- English
Similar Records
Apparatus and method for synchronization of a coprocessor unit in a pipelined central processing unit
Vector processing unit
Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan
Patent
·
Tue Jul 24 00:00:00 EDT 1990
·
OSTI ID:6473540
Vector processing unit
Patent
·
Mon Dec 12 23:00:00 EST 1988
·
OSTI ID:6337994
Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan
Patent
·
Tue Mar 20 00:00:00 EDT 2012
·
OSTI ID:1039559