Instruction execution accelerator for a pipelined digital machine with virtual memory
This patent describes a pipelined digital machine for the high speed processing of instructions of a programmed sequence stored in a memory, the digital machine comprising: means for fetching instructions of the programmed sequence from the memory; means, coupled to the fetching means, for decoding instructions into operational commands; means, coupled to the decoding means, for issuing instructions generating the operational commands in a timed sequence; means for executing instructions by operating on the operational commands in response to their issue from the issuing means, and indicating to the issuing means that the operational commands have been executed; means, coupled to the determining means and to the issuing means, for determining whether or not at least one portion of the execution of the operational commands of the previously issued instruction can occur asynchronously to the execution of the operational commands of the previously decoded instruction waiting to issue, and means, coupled to the determining means and to the issuing means, for accelerating the execution of the programmed sequence in advance of the indication from the executing means that the operational commands of the previously issued instruction have been executed by causing the issuing means to issue the operational commands of the previously decoded instruction in response to an affirmative determination by the determining means.
- Assignee:
- Intergraph Corp., Huntsville, AL
- Patent Number(s):
- US 4811215
- OSTI ID:
- 5979325
- Resource Relation:
- Patent File Date: Filed date 12 Dec 1986
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
ARRAY PROCESSORS
SUPERCOMPUTERS
DIGITAL SYSTEMS
COMPUTER ARCHITECTURE
DIGITAL COMPUTERS
EFFICIENCY
EXECUTIVE CODES
MEMORY DEVICES
MEMORY MANAGEMENT
PARALLEL PROCESSING
COMPUTER CODES
COMPUTERS
PROGRAMMING
990210* - Supercomputers- (1987-1989)