Preemptive scheduling of a multiprocessor system with memories to minimize maximum lateness

Journal Article · Thu Nov 01 00:00:00 EST 1984 · SIAM J. Comput.; (United States)

DOI:https://doi.org/10.1137/0213043· OSTI ID:5914700

Lai, T H; Sahni, S

The authors develop an O(q/sup 2/n + n log n) algorithm to obtain a preemptive schedule that minimizes maximum lateness when n jobs with given due dates and memory requirements are to be scheduled on m processors (n greater than or equal to m) of given memory sizes q is the number of distinct due dates. The value of the minimum maximum lateness can itself be found in O(qn + n log n) time.

• Research Organization: Department of Computer Science, University of Minnesota, Minneapolis, Minnesota 55455.
• OSTI ID: 5914700
• Journal Information: SIAM J. Comput.; (United States), Vol. 13:4
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
SUPERCOMPUTERS
ALGORITHMS
MEMORY DEVICES
SCHEDULES
COMPUTER CALCULATIONS
TIME DEPENDENCE
COMPUTERS
DIGITAL COMPUTERS
MATHEMATICAL LOGIC
990200* - Mathematics & Computers