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Electrical, thermal, and architecture aspects of VLSI packaging and interconnects for high-speed digital computers

Thesis/Dissertation ·
OSTI ID:5896511
Packaging and interconnects for Very Large Scale Integration (VLSI) integrated circuits have become problematic as chip power levels, Input/Output (I/O) counts, and signal speeds have increased. This work addresses several important aspects of the packaging/interconnect problem in four major parts. In the first part, an analysis of the fundamental performance limitations imposed by system packaging is presented. In part two, the effect of package geometry on thermal resistance is studied for a group of conventional and novel packages. Thermal resistance is determined using electrothermal networks (variation of finite difference method) for free convection, forced air, forced liquid and microchannel cooling. The third part of this work is dedicated to description of a new hierarchical model for an idealized digital electronic system. This model permits quantitative simulations of packaging performance. The fourth and final section of this work details the design, fabrication, and testing of a new glass-ceramic multichip module test vehicle. This effort is intended to determine the electrical, thermal, and materials properties of a new glass-ceramic material, and the assess the utility of this material in a multichip module technology. Design, layout, silicon test chip processing, and electrical testing are described in detail. Test results demonstrate improved signal propagation speed, noise properties, and chip-to-substrate thermal mismatch relative to conventional packaging materials.
Research Organization:
Cornell Univ., Ithaca, NY (USA)
OSTI ID:
5896511
Country of Publication:
United States
Language:
English