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Implementation studies for a VLSI Prolog coprocessor

Journal Article · · IEEE Micro; (United States)
OSTI ID:5865460
Prolog, like other declarative languages, requires the development of new execution models that are more complex than the ones supporting imperative languages. New primitives related to the management of the search strategy and the unification process must be identified. Moreover, to achieve better performance, time-critical primitives must be moved into hardware. Adding a specialized coprocessor to a standard CPU obtains one of the most effective implementations; this method also allows a modular upgrade of existing systems. A Prolog coprocessor behaves differently than numerical coprocessors. It does not execute single instructions; it executes complete segments of Prolog code. The approach the authors describe here refers to a 32-bit coprocessor designed as one VLSI (very large scale integrated) circuit based on microprogrammed architecture. The most innovative aspect of this project is the fully dedicated microarchitecture of the execution unit. The authors performed a detailed analysis and simulated the computational model and its implementation for data to support their final design decisions. They developed the analysis considering two execution techniques: interpreted and compiled. They describe compiled execution selected for the final design. Their simulations trace the actual behavior of the execution model and point out the performance that can be obtained using different architectural solutions. These results permit the selection of an optimal architecture within the technological constraints of VLSI implementation.
Research Organization:
Elsag S.p.A. (IT)
OSTI ID:
5865460
Journal Information:
IEEE Micro; (United States), Journal Name: IEEE Micro; (United States) Vol. 9:1; ISSN IEMID
Country of Publication:
United States
Language:
English