Analysis and comparison of cache coherence protocols for a packet-switched multiprocessor

Journal Article · Tue Aug 01 00:00:00 EDT 1989 · IEEE Trans. Comput.; (United States)

DOI:https://doi.org/10.1109/12.30868· OSTI ID:5806929

Yang, Q; Bhuyan, L N; Liu, B C

The use of private caches in a multiprocessor system causes inconsistency of the shared data among the caches and among caches and the main memory. A large number of protocols have been proposed to solve this coherence problem. In this paper, the authors develop analytical models for seven existing cache protocols, namely: Write-Once, Write-Through, Synapse, Berkeley, Illinois, Firefly, and Dragon. The protocols are implemented on a multiprocessor with a packet-switched shared bus. The models are based on queueing networks that consist of both open and closed classes of customers. The models incorporate the requests for invalidation signals, write-through, and write-back operations and the solution is based on the mean value analysis (MVA) algorithm. Performance comparison among these protocols under various system parameters is carried out based on our models.

• Research Organization: Rhode Island Univ., Kingston, RI (USA). Dept. of Electrical Engineering; University of Southwestern Louisiana, Lafayette, LA (USA)
• OSTI ID: 5806929
• Journal Information: IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. 38:8; ISSN ITCOB
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ANALYTICAL SOLUTION
ARRAY PROCESSORS
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PARAMETRIC ANALYSIS
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QUEUES