Parallel algorithms with processor failures and delays. Technical report

Technical Report · Thu Aug 01 04:00:00 EDT 1991

OSTI ID:5796465

Buss, J F; Kanellakis, P C; Radge, P L; Shvartsman, A A

The authors study efficient deterministic parallel algorithms on two models: restartable fail-stop CRCW PRAMs and strongly asynchronous PRAMs. In the first model, synchronous processors are subject to arbitrary stop failures and restarts determined by an on-line adversary and involving loss of private but not shared memory; the complexity measures are completed work (where processors are charged for completed fixed-size update cycles) and overhead ratio (completed work amortized over necessary work and failure). In the second model, the result of the computation is a serialization of the actions of the processors determined by an on-line adversary; the complexity measure is total work (number of steps taken by all processors). Despite their differences the two models share key algorithmic techniques. They present new algorithms for the Write-All problem (in which P processors write ones into an array of size N) for these two models. These algorithms can be used to implement a simulation strategy for any N processor PRAM on a restartable fail-stop P processor CRCW PRAM such that it guarantees a terminating execution of each simulated N processor step, with O(log sq N) overhead ratio.

• Research Organization: Brown Univ., Providence, RI (United States). Dept. of Computer Science
• OSTI ID: 5796465
• Report Number(s): AD-A-242764/9/XAB; CS--91-54; CNN: N00014-91-J-1613; NSF-IRI-8617344
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ALGORITHMS
ARRAY PROCESSORS
FAILURES
MATHEMATICAL LOGIC
MEMORY DEVICES
MEMORY MANAGEMENT
PARALLEL PROCESSING
PROGRAMMING
SIMULATION