Formal verification of properties of digital systems using an automated reasoning system

Conference · Tue Dec 31 23:00:00 EST 1985

OSTI ID:5760673

Kljaich, J; Wojcik, A S; Smith, B T

This paper describes a part of an ongoing research project whose goal is to develop a formal design verification system based on the use of ITP, an LMA (Logic Machine Architecture) based Interactive Theorem Prover developed at Argonne National Laboratory. Specifically, a Petri net representation for systems is described together with the ITP implementation of a rule-based system for the manipulation of system descriptions. To illustrate the representation and the capabilities of the system under development, the Draper Laboratories Fault-Tolerant Processor is used as an example. Results concerning the formal verification of the fault-tolerant properties of this system are described. 17 refs., 7 figs.

• Research Organization: Argonne National Lab., IL (USA); Michigan State Univ., East Lansing (USA). Dept. of Computer Science
• DOE Contract Number: W-31109-ENG-38
• OSTI ID: 5760673
• Report Number(s): CONF-860678-1; ON: DE86005552
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ARRAY PROCESSORS
ARTIFICIAL INTELLIGENCE
COMPUTERIZED SIMULATION
DATA-FLOW PROCESSING
FAULT TREE ANALYSIS
PROGRAMMING
SIMULATION
SYSTEM FAILURE ANALYSIS
SYSTEMS ANALYSIS