Formal verification of digital systems
A vital need brought on by the continuing VLSI revolution is the development of computer-aided tools that help to ameliorate the difficulties faced by logic designers when they are required to verify properties about their designs. Recently, interest has grown in the possibility of developing alternatives to standard simulation as a means of dealing with this problem. Several researchers suggest that use of artificial intelligence techniques as such an alternative. This thesis develops a framework under which formal verification tools can be developed and evaluated and describes a specific tool that uses an automated reasoning system together with Petri nets for analyzing and modeling digital systems at various levels of abstraction. This thesis expands the previous work in this area along several dimensions: (1) a more generic representation and methodology that permits the hierarchical verification of a wider range of properties of digital systems; (2) employment of a notation that provides coherence between various design verification tools, and models the linkage between software and hardware; and (3) demonstration of the above with a specific implementation that formally verifies realistic systems by utilizing an interactive theorem prover, ITP, based on a reasoning package developed at Argonne National Laboratory called Logic Machine Architecture (LMA).
- Research Organization:
- Illinois Inst. of Tech., Chicago (USA)
- OSTI ID:
- 5488450
- Country of Publication:
- United States
- Language:
- English
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