Storage selection override apparatus for a multimicroprocessor implemented data processing system
A multiprocessor storage selection override data processing system is described which consists of: primary processor means for generating an instruction fetch signal or an operand access signal indicative of the fetch of an instruction and the retrieval of an operand, respectively, and for executing a selected set of instructions; secondary processor means for executing a set of instructions which is different than the set of instructions executed by the primary processor means; processor switch means connected to the primary and secondary processor means on one other side for switching on one of the processor means in response to an output signal from the other of the processor means thereby rendering idle the other of the processing means; latch means connected to the primary and secondary processor means for switching to a set or a reset condition in response to an output signal from the one of the processor means; logic circuit means connected to the latch means and to the primary and secondary processor means for developing an output signal in response to the set condition from the latch means and to the instruction fetch signal from the primary processor means or in response to the set condition from the latch means and to the operand access signal from the primary processor means or in response to an output signal from the primary or secondary processor means; main storage means connected to the logic circuit means; and control storage means connected to the logic circuit means, the control storage means including private storage means.
- Assignee:
- International Business Machines Corp., Armonk, NY
- Patent Number(s):
- US 4591982
- OSTI ID:
- 5676307
- Resource Relation:
- Patent File Date: Filed date 29 Aug 1983
- Country of Publication:
- United States
- Language:
- English
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