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A comprehensive methodology for algorithm characterization, regularization and mapping into optimal VLSI arrays

Thesis/Dissertation ·
OSTI ID:5533956
This dissertation provides a fairly comprehensive treatment of a broad class of algorithms as it pertains to systolic implementation. The authors describe some formal algorithmic transformations that can be utilized to map regular and some irregular compute-bound algorithms into the beat fit time-optimal systolic architectures. The resulted architectures can be one-dimensional, two-dimensional, three-dimensional or nonplanar. The methodology detailed in the dissertation employs, like other methods, the concept of dependence vector to order, in space and time, the index points representing the algorithm. However, by differentiating between two types of dependence vectors, the ordering procedure is allowed to be flexible and time optimal. Furthermore, unlike other methodologies, the approach reported here does not put constraints on the topology or dimensionality of the target architecture. The ordered index points are represented by nodes in a diagram called Systolic Precedence Diagram (SPD). The SPD is a form of precedence graph that takes into account the systolic operation requirements of strictly local communications and regular data flow. Therefore, any algorithm with variable dependence vectors has to be transformed into a regular indexed set of computations with local dependencies. This can be done by replacing variable dependence vectors with sets of fixed dependence vectors. The SPD is transformed into an acyclic, labeled, directed graph called the Systolic Directed Graph (SDG). The SDG models the data flow as well as the timing for the execution of the given algorithm on a time-optimal array.
Research Organization:
Louisiana State Univ. and Agricultural and Mechanical Coll., Baton Rouge, LA (United States)
OSTI ID:
5533956
Country of Publication:
United States
Language:
English