Automatic test pattern generation for logic circuits using the Boolean tree

Thesis/Dissertation · Tue Jan 01 04:00:00 EST 1991

OSTI ID:5412969

Jeong, Taegwon

The goal of this study was to develop an algorithm that can generate test patterns for combinational circuits and sequential logic circuits automatically. The new proposed algorithm generates a test pattern by using a special tree called a modified Boolean tree. In this algorithm, the construction of a modified Boolean tree is the most time-consuming step. Following the construction of a modified Boolean tree, a test pattern can be found by simply assigning a logic value 1 for even primary inputs and a logic value 0 for odd primary inputs of the constructed modified Boolean tree. The algorithm is applied to several benchmark circuits. The results showed the following: (1) for combinational circuits, the algorithm can generate test patterns 10-15% faster than the FAN algorithm, which is known as one of the most efficient algorithms to-date; (2) for sequential circuits, the algorithm shows more fault coverage than the nine valued algorithm.

• Research Organization: Florida Univ., Gainesville, FL (United States)
• OSTI ID: 5412969
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
426000* -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
ALGORITHMS
BENCHMARKS
DECISION TREE ANALYSIS
ELECTRONIC CIRCUITS
LOGIC CIRCUITS
MATHEMATICAL LOGIC
PATTERN RECOGNITION
TESTING