Method for making a CMOS circuit having a reduced tendency to latch by controlling the band-gap of source and drain regions
Patent
·
OSTI ID:5401251
This patent describes a CMOS integrated circuit comprising complementary NMOS and PMOS transistors formed on a substrate, a method for reducing the tendency of the circuit to latch comprising the step of implanting ions into the source region of each of the NMOS and PMOS transistors, the ions being of a material having an energy gap which is lower than the energy gap of the material forming the substrate.
- Assignee:
- Fairchild Conductor Corp., Cupertino, CA
- Patent Number(s):
- US 4603471
- OSTI ID:
- 5401251
- Country of Publication:
- United States
- Language:
- English
Similar Records
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Related Subjects
42 ENGINEERING
420800* -- Engineering-- Electronic Circuits & Devices-- (-1989)
CHARGED PARTICLES
DRAINAGE
ELECTRONIC CIRCUITS
FABRICATION
FASTENING
GRADED BAND GAPS
INTEGRATED CIRCUITS
ION IMPLANTATION
IONS
JOINING
MICROELECTRONIC CIRCUITS
MOS TRANSISTORS
SEMICONDUCTOR DEVICES
SUBSTRATES
TRANSISTORS
420800* -- Engineering-- Electronic Circuits & Devices-- (-1989)
CHARGED PARTICLES
DRAINAGE
ELECTRONIC CIRCUITS
FABRICATION
FASTENING
GRADED BAND GAPS
INTEGRATED CIRCUITS
ION IMPLANTATION
IONS
JOINING
MICROELECTRONIC CIRCUITS
MOS TRANSISTORS
SEMICONDUCTOR DEVICES
SUBSTRATES
TRANSISTORS